Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. One of the most commonly known flash memories is the one-transistor flash memory, wherein each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide (tunneling oxide). Each of the memory cells can be electrically charged by injecting electrons from the drain region through the tunneling oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the substrate through the tunneling oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of charges in the floating gate.
It is highly desirable to scale down write/erase voltages of flash memory, which has typically been achieved by decreasing the thickness of the tunneling oxide layer. However, conventional one-transistor flash memory has a conductive storage layer, and thus thin tunneling oxide layers will cause a significant leakage problem. Stored charges are more likely to be leaked to the substrate through a thin tunneling oxide layer than through a thick tunneling oxide layer. Particularly, if there is a defect in the tunneling oxide layer, all stored charges can potentially leak through the defect since charges can flow freely in the floating gate.
One method for reducing the thickness of the tunneling oxide layer without causing severe charge loss is using a (poly-)Si—SiO2—SiN—SiO2—Si (SONOS) structure. FIG. 1 illustrates a SONOS flash memory cell. A tunneling oxide layer 2 is formed on a silicon substrate 10. A silicon nitride layer (floating gate) 4 is on the tunneling oxide layer 2. Silicon nitride layer 4 comprises local traps for trapping and storing charges representing digital data “1” or “0.” A blocking oxide 6 is formed on the floating gate 4 to prevent charges from a possible leakage from reaching gate electrode 8, which is typically formed of polysilicon.
In SONOS memory cells, charges are stored inside the discrete and electrically isolated traps of nitride (SiN), while only the trapped charges close to the oxide defects can leak out. The good electrical isolation of stored charges is different from the conventional continuous polysilicon floating gate, which may have all stored charges leak out through a defect in the tunneling oxide layer. Therefore, it is possible to significantly scale down the thickness of the tunneling oxide layer 2, for example, to between about 2 nm and about 2.5 nm, while the charge retention ability is not noticeably compromised. In addition, with the reduction of the thickness of the tunneling oxide layer, write/erase voltages can be lowered.
The above-discussed features of SONOS memory cells make them good candidates for being integrated with CMOS logic and used for embedded system-on-chip (SoC) applications. However, further improvements are needed to simultaneously achieve low operation voltage, long data retention and fast write/erase speed in order to make them fully compatible with existing CMOS logic.
Although the SONOS memory devices provide a potential solution for down-scaling the tunneling oxide layer below conventional memory devices with a poly floating gate, it is still challenging to scale the write/erase voltage below 5 V and maintain the required ten year data retention. Additionally, the conventional SONOS memory devices using silicon nitride as storage have the disadvantage of great conduction band discontinuity (ΔEC) with a silicon channel. As a result, charge leakage is still a problem and data retention time is adversely affected. To overcome these problems, relatively thick oxides are typically needed. However, thick oxides will cause an increase in write/erase voltages.
Accordingly, what is needed in the art is a flash memory cell that may incorporate electrically isolated traps in the storage layer to take advantage of the benefits thereof while at the same time overcoming the deficiencies of the prior art.